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FEDL60852A-03
1 Semiconductor ML60852A
USB Device Controller
This version:
Nov. 2001
Previous version: Oct. 2001
GENERAL DESCRIPTION
The ML60852A is a general purpose Universal Serial Bus (USB) device controller. The ML60852A provides a USB serial interface engine, USB transceiver, FIFOs, control/status registers, application interface circuit, and oscillation circuit thereby easily realizing a USB system. The ML60852A supports four types of data transfer such as control transfer, bulk transfer, interrupt transfer and isochronous transfer, and also supports five or six endpoints.
FEATURES
* * * * USB1.1 compliant Supports full-speed (12 Mbps). Supports four types of transfer; control transfer, bulk transfer, interrupt transfer, and isochronous transfer. Endpoints: 5 to 6 endpoints Control EP 1 Bulk/interrupt EP 3 Isochronous/bulk/interrupt EP 1 or 2 Built-in FIFO for data storage A two-layer configuration of FIFO for each of EP1, EP2, EP4, and EP5 8/16 bit DMA supported (EP1, EP2, EP4, and EP5) Intelligent Serial Interface Engine (SIE) Supports bus-powered device. The suspend condition is automatically detected and the low-power mode is activated. Normal operation is automatically restarted when the resume condition is detected. Built-in USB transceiver circuit Ta = -20 to +80 C VCC=3.0 to 3.6 V Interface with 5 V circuit is possible. (Input: 5 V tolerant, output: TTL) Built-in 12 MHz /6 MHz oscillation circuit Package options: 44-pin plastic TQFP 56-pin plastic LGA
* * * * * * * * * * *
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Endpoints and FIFOs By initializing appropriate registers, the ML60852A can be operated in either 5EP or 6EP mode. Although the transfer mode that can be used by EP0 is fixed, it is possible to select either the bulk transfer mode or the interrupt transfer mode for end points EP1, EP2, and EP3, and one of the modes of isochronous, bulk, or interrupt transfer can be selected for EP4 and EP5. In addition, it is possible to selectively set the direction of data transfer for EP1 to EP5.
End point EP0 EP1 EP2 EP3 EP4 FIFO Capacity Reception 32 Transmission 32 64x2 64x2 32 512x2 (64x2) EP5 -- Bulk/interrupt transfer (IN/OUT) Bulk/interrupt transfer (IN/OUT) Bulk/interrupt transfer (IN/OUT) Isochronous/bulk/ interrupt transfer (IN/OUT) -- 256x2 (64x2) DMA Possible DMA Possible DMA Possible 5EP Mode Transfer mode Control transfer Remarks FIFO Capacity Reception 32 Transmission 32 64x2 64x2 32 256x2 (64x2) Bulk/interrupt transfer (IN/OUT) Bulk/interrupt transfer (IN/OUT) Bulk/interrupt transfer (IN/OUT) Isochronous/bulk/ interrupt transfer (IN/OUT) Isochronous/bulk/ interrupt transfer (IN/OUT) DMA Possible DMA Possible DMA Possible DMA Possible 6EP Mode Transfer mode Control transfer Remarks
FIFO Capacity: The unit is bytes. Note 1: The selection between the 5EP mode and the 6EP mode is made by bit D2 of the register SYSCON. Note 2: EP3 permits rate feedback data sequence toggling. Note 3: EP1, EP2, and EP3 are all mutually independent, and can be assigned for bulk transfer or interrupt transfer individually. It is possible to set the maximum packet size up to 64 bytes (32 bytes for EP3) during both bulk transfer and interrupt transfer. Note 4: It is possible to set EP4 and EP5 to one of the modes of isochronous transfer, bulk transfer, and interrupt transfer. The maximum packet size can be up to 64 bytes when these end points are set to bulk transfer. Note 5: When using EP4 and EP5 in the isochronous transfer mode: In the 5EP mode, the maximum packet size of EP4 is 512 bytes. EP5 cannot be used. In the 6EP mode, the maximum packet size of both EP4 and EP5 is 256 bytes.
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PIN CONFIGURATION (TOP VIEW)
44-pin TQFP (Top View)
XL XB
DACK0 A0 A1 A2 A3 A4 A5 A6 DREQ1 ADSEL ALE/PUCTL DREQ0 AD7 AD6 AD5 AD4 GND VCC AD3 AD2 AD1 AD0 34 35 36 37 38 39 40 41 42 43 44 33 32 31 30 29 28 27 26 25 24 23
YL
YB
22 21 20 19 18 17 16 15 14 13 12
D8 D9 D10 D11 DACK1 TEST2 D12 D13 D14 D15 INTR
Package dimensions (unit: mm) 44TQFP XB XL YB YL Height Lead pitch 10.0 0.1 12.0 0.2 10.0 0.1 12.0 0.2 1.2MAX 0.8
D+ DVCC TEST1 GND XIN XOUT CS RD WR RESET
1 2 3 4 5 6 7 8 9 10 11
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56-pin LGA (Top View)
INTR
NC ALE/ PUCTL DREQ1
D8
D9
D11
TEST2
D12
D14
NC
NC
D10
DACK1
NC
D13
D15
NC
RESET
ADSEL
RD
WR
A5
A6
XOUT
CS
A4
NC
NC
XIN
A2
A3
TEST1
GND
A0
A1
Pin No.1 Marking
AD7 AD5 NC VCC AD2
D-
VCC
DACK0
NC
NC
D+
NC
DREQ0
AD6
AD4
GND
AD3
AD1
AD0
NC
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PIN DESCRIPTION
Pin name D+, DXIN, XOUT AD7:AD0 A6:A0 D15:D8 CS RD WR INTR DREQ0 DREQ1 DACK0 DACK1 ALE/PUCTL ADSEL RESET TEST1, TEST2 VCC GND Pin count 2 2 8 7 8 1 1 1 1 1 1 1 1 1 1 1 2 2 2 44 I/O I/O -- I/O I I/O I I I O O O I I I,O I I I USB data Pins for external crystal Data bus (LSB)/address inputs Address inputs Data bus (MSB) Chip select signal input pin. Active "L" Read signal input pin. Active "L" Write signal input pin. Active "L" Interrupt request signal output pin DMA0 request output pin DMA1 request output pin DMA0 reception signal input pin DMA1 reception signal input pin Address latch enable signal input pin/pull-up control pin Address input format select input pin Reset signal input pin Test pin. (Normally at "L") 3.3 V power supply pin GND Description
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BLOCK DIAGRAM
6/12 MHz
XIN
Register Set
6/12 MHz Oscillator 8-byte Setup Register A6:A0
XOUT Application Interface AD8:AD0 D15:D8
Multiplication Circuit EP0 EP0 Transmit Receive FIF0 FIF0
Local MCU
Consult with a crystal maker for crystal peripheral parts Protocol Engine EP1 FIF0
CS WR,RD RESET INTR
ALE/PUCTL
EP2 FIF0
DREQ0,1 DACK0,1
1.5 k EP3 FIF0
D+ USB Transceiver EP4 EP5 FIF0
22
22
D-
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Input Voltage (Tolerant) Input Voltage (Normal) Storage Temperature Symbol VCC VIT VI TSTG Condition VSS = 0 V TJ = 25C -- Rating -0.3 to + 4.6 -0.3 to + 6.0 -0.3 to + VCC + 0.3 -65 to + 150 Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Operating Temperature Oscillation Frequency Symbol VCC VOP FOSC Condition -- -- -- Range 3.0 to 3.6 -20 to 80 120.03 or 60.015 Unit V C MHz
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ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VCC = 3.0 to 3.6 V, Ta = -20 to +80 C) Parameter High-level Input Voltage Low-level Input Voltage High-level Input Voltage Low-level Input Voltage Schmitt Trigger Input Voltage High-level Output Voltage Low-level Output Voltage High-level Input Current Low-level Input Current 3-state Output Leakage Current Power Supply Current (Operating) Power Supply Current (Standby) Symbol VIH VIL VIH VIL Vt+ VtVt VOH VOL IIH IIL IOZH IOZL ICC ICCS Condition -- -- -- -- -- -- (Vt+) - (Vt-) IOH = -100 A IOH = -4 mA IOL = 100 A IOL = 4 mA VIH = VCC VIL = 0V VOH = VCC VOL = 0V -- Note 4(~50C) Note 4(~80C) Min. 2.1 -0.3 VCC x 0.8 -0.3 -- 0.7 0.4 VCC - 0.2 2.4 -- -- -- -10 -- -10 -- -- -- Typ. -- -- -- -- 1.5 1.0 0.5 -- -- -- -- 0.1 -0.1 0.1 -0.1 -- -- -- Max. 5.5 -0.7 VCC + 0.3 VCC x 0.2 2.0 -- -- -- -- 0.2 0.45 10 -- 10 -- 50 60 400 Unit V Note 1 V V XIN V V V V V V V V A Note 3 A A A mA A D15:D8 AD7:AD0 VCC VCC Note 2 RESET Applicable pin
Notes: 1. Applied to D15: D8, AD7: AD0, A6: A0, CS, RD, WR, DACK0, DACK1, ALE, and ADSEL. 2. Applied to D15: D8, AD7: AD0, A6: A0, INTR, DREQ0, DREQ1 and ALE/PUCTL 3. Applied to XIN, AD7: AD0, CS, RD, WR, DACK, ALE, and ADSEL. 4. The XIN pin is fixed at a high level or a low level in the suspend state. All the output pins are open.
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DC Characteristics (2) USB Port
(VCC = 3.0 to 3.6 V, Ta = -20 to +80 C) Parameter Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold High-level Output Voltage Low-level Output Voltage Output Leakage Current Symbol VDI VCM VSE VOH VOL ILO Condition (D+) - (D -) Includes VDI range -- RL of 15 k to GND RL of 1.5 k to 3.6 V 0 V AC Characteristics USB Port
(VCC = 3.0 to 3.6 V, Ta = -20 to +80 C) Parameter Rise Time Fall Time Output Signal Crossover Voltage Driver Output Resistance Data Rate Symbol tR tF VCRS ZDRV TDRATE Condition CL = 50 pF CL = 50 pF -- Steady State Driver Ave. Bit Rate (12 Mbps 0.25%) Min. 4 4 1.3 28 11.97 Typ. -- -- -- -- -- Max. 20 20 2 44 12.03 Unit ns ns V D+, D Mbps Applicable pin
Notes: 1. 1.5 k pull-up to 3.3 V on the D + data line.
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SIGNAL DESCRIPTIONS
USB Interface
Signal Type Assertion Description USB data (Plus). This signal and the D- signal are the transmitted or received data from/to USB Bus. The table below shows values and results for these signals. D+ D+ I/O -- 0 0 1 1 D0 1 0 1 Result Single end 0 Differential "0" Differential "1" Undefined
D-
I/O
--
USB Data (Minus). This signal and the D+ signal are the transmitted or received data from/to USB Bus. The table above shows values and results for these signals.
Crystal Oscillator Interface
Signal XIN XOUT Type I O Assertion -- -- Description For internal oscillation, connect a crystal to XIN and XOUT. For external oscillation, supply an external 12 MHz clock signal to XIN. Set XOUT to be open.
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Application Interface
Signal D15: D8 AD7: AD0 A6: A0 CS RD WR INTR DREQ0 DREQ1 DACK0 DACK1 Type I/O I/O I I Assertion -- -- -- LOW Upper byte (MSB) of data bus. Lower byte (LSB) of data bus when ADSEL is LOW. Address and lower byte of data bus are multiplexed when ADSEL is HIGH. Address when ADSEL is LOW. Chip Select. When this signal is asserted LOW, the ML60852A is selected and ready to read or write data. This signal is invalid in single address mode during DMA transfer. Read Strobe. When this signal is asserted LOW, the Read instruction is executed. Write Strobe. When this signal is asserted LOW, the Write instruction is executed. Interrupt Request. When this signal is asserted, the ML60852A makes an interrupt request to the application. DMA Request. This signal requests the DMA0 to make a DMA transfer. DMA Request. This signal requests the DMA1 to make a DMA transfer. DMA Acknowledge Signal for DREQ0. This signal, when asserted, enables accessing FIFOs, without address bus setting. DMA Acknowledge Signal for DREQ1. This signal, when asserted, enables accessing FIFO, without address bus setting. When ADSEL is HIGH, the address and CS on AD7: AD0 are latched at the trailing edge of this signal. D+ pull-up resistor connection output when ADSEL is LOW. VCC potential when bit D3 of SYSCON register is "1", and high-impedance when it is "0". ADSEL I -- When ADSEL is LOW, the address is input on A6: A0 and data is input on AD7: AD0. When ADSEL is HIGH, address and data are multiplexed on AD7: AD0. System Reset. When this signal is asserted LOW, the ML60852A is reset. RESET I LOW When the ML60852A is powered on, this signal must be asserted for 1 s or more. Description
I I O O O I I
LOW LOW (Note 1) (Note 1) (Note 1) (Note 2) (Note 2)
ALE/PUCTL
I or O
HIGH
Notes: 1. The assertion polarity can be modified by appropriately initializing the polarity selection register (POLSEL). The default is LOW. 2. The assertion polarity can be modified by appropriately initializing the polarity selection register (POLSEL). The default is HIGH.
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FUNCTIONAL DESCRIPTIONS
(1) USB Interface The ML60852A is a USB device controller. The ML60852A provides the following functions which are bases for a USB protocol. Therefore, the application can process a lot of its own functions. * Bit synchronization * Encoding and decoding NRZI signals. * Generating and detecting Sync bytes. * Bit stuffing * Generating and checking CRCs (CRC5, CRC16). * Encoding and decoding PID (packet identifier). 1. Decoding token. 2. Encoding and decoding handshake. * Generating and detecting SOP and EOP. * Enpacket (packing) and depacket (unpacking) * Comparing device addresses. * Storing 8-byte setup data from a host into the setup register. * Transmitting data in transmit FIFO. * Storing receive data into receive FIFO of the corresponding endpoint. (2) USB Transfer Modes The ML60852A supports four kinds of transfer modes such as control transfer mode , interrupt transfer mode, bulk transfer mode, and isochronous transfer mode, which are specified by USB Standards. (a) Control transfer mode is used to receive and respond to configurations and commands from a host, and to exchange status information between the host and peripherals. (b) Bulk transfer mode is used for transferring large amounts of data in a limited time period when sufficient USB bus resources become available. (c) Interrupt transfer mode is used for transferring moderate amounts of data in a specified amount of time. (d) The isochronous transfer mode is used to continuously transfer audio data, moving pictures data and other data. (e) Isochronous transfer mode is used for streaming, real time data transfers such as audio or video.
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(3) Endpoints and FIFOs In the ML60852A, it is possible to select, by making appropriate setting in the SYSCON register, the 5EP mode in which there are five end points or the 6EP mode in which there are six end points. Although the transfer mode that can be used by EP0 is fixed, it is possible to select either the bulk transfer mode or the interrupt transfer mode for the end points EP1, EP2, and EP3, and one of the modes of isochronous, bulk, or interrupt transfer can be selected for EP4 and EP5. In addition, it is possible to selectively set the direction of data transfer for EP1 to EP5.
End point EP0 EP1 EP2 EP3 EP4 EP5 FIFO Capacity Reception 32 Transmission 32 64x2 64x2 32 512x2 (64x2) -- B/Int (IN/OUT) B/Int (IN/OUT) B/Int (IN/OUT) Iso/B/Int (IN/OUT) -- DMA Possible 256x2 (64x2) 256x2 (64x2) DMA Possible DMA Possible Rate 5EP Mode Transfer mode C Remarks FIFO Capacity Reception 32 Transmission 32 64x2 64x2 32 B/Int (IN/OUT) B/Int (IN/OUT) B/Int (IN/OUT) Iso/B/Int (IN/OUT) Iso/B/Int (IN/OUT) DMA Possible DMA Possible DMA Possible DMA Possible Rate 6EP Mode Transfer mode Control transfer Remarks
FIFO Capacity: The unit is bytes. Note: Transfer modes: C = Control transfer B = Bulk transfer Int = Interrupt transfer Iso = Isochronous transfer Rate = Compatible with data sequence toggling of rate feedback.
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(4) Operation of Control Transfer Control transfer is the default transfer mode for host-device communications as outlined in USB specifications. Control transfer uses structured message pipes and is composed of the following three stages: (a) Setup stage In this stage, a setup token and 8 bytes of setup data are transmitted from the host. The ML60852A decodes the setup token, and automatically stores the 8 bytes of setup data in the setup register. When this is completed normally, the ML60852A returns ACK to the host. The 8-byte setup data is the standard request code defined in Section 9.3 of the USB Standards, or a code of the requests unique to each device class, etc. The request is decoded on the local MCU side. (b) Data stage If the request specified by the 8-byte setup data is also accompanied by transfer of parameter data from the host to the device, the transfer is a control write transfer, and the OUT token and the data packet are transmitted from the host. When these are received normally, the ML60852A stores the parameter data in the EP0 receive FIFO and returns ACK to the host. If the request is accompanied by transfer of parameter data from the device to the host, the transfer is a control read transfer, and when the host sends the IN token, the ML60852A sends the parameter data that was already stored beforehand in the EP0 transmit FIFO by the local MCU. When the host receives this normally, it returns an ACK to the ML60852A. On the other hand, in the case of requests that do not contain any parameter data that need to be transmitted or received, data stage will not be present and the processing proceeds directly to the status stage from the setup stage. (c) Status stage The status stage is a stage intended for reporting the status of the result of executing a request from the device to the host. During a control write transfer or a control transfer without data, an IN token is sent by the host, and the ML60852A returns a response to it. During a control read transfer, an OUT token and a zero length packet (ZLP) is sent by the host, and the ML60852A returns a response to it. During the above control transfers, the local MCU needs only to read from or write to the 8-byte setup registers mapped at 00h to 07h, the EP0 transmit FIFO mapped at 70h, and the EP0 receive FIFO mapped at 78h according to the interrupt cause, and all other operations will be carried out automatically by the ML60852A.
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(5) Data packet transmission and reception procedure during bulk transfer and interrupt transfer modes The ML60852A is normally used on the peripheral device side. In this method of use, the ML60852A is connected on one side to the host via the USB bus and is connected on the other side via a parallel interface to the local microcontroller (local MCU) inside the peripheral device. Transfer of data is the major function in all types of transfer modes other than the control transfer mode. When carrying out transfer of data packets between the ML60852A and the host, the following packet communication is carried out via the USB bus for data transfer of each packet. (a) Token packet transfer (IN token or OUT token) from the host to the ML60852A. (b) Data packet transfer in the desired direction (from the host to the device or from the device to the host). (c) Transfer of handshake packet in a direction opposite to that of the data packet. When packet transfer is completed normally, an ACK packet is returned in step (c) and the operation proceeds to the next packet transfer. The ML60852A requests the local MCU to transmit or receive a packet of data by asserting the INTR pin. The interrupt cause will be "packet ready". The transmit packet ready interrupt is one that requests that the packet of data to be transmitted be written in the transmit FIFO, and the receive packet ready interrupt is one that requests the local MCU to read out the data that has been received and stored in the receive FIFO. The above procedures of transferring one packet of data are explained below for transmission and reception separately. 1) During transmission The local MCU writes one packet of data that has to be transmitted in the transmit FIFO of the corresponding EP in the ML60852A, and sets the transmit packet ready bit of the corresponding EP status register of the ML60852A. When the host transmits an IN token packet to the ML60852A, the ML60852A transmits to the host the data packet stored in the above transmit FIFO. When the host receives one data packet normally, it returns an ACK packet to the ML60852A. Consequently, the ML60852A resets the transmit packet ready status, thereby completing the transfer of one data packet over the USB bus. When the transmit packet ready status is reset, the ML60852A gives a request to the local MCU in terms of a transmit packet ready interrupt thereby prompting the local MCU to write the next packet of data to be transmitted. 2) During reception The host sends to the ML60852A an OUT token followed by a data packet. The ML60852A stores the received data packet in the receive FIFO of the corresponding EP. When it is confirmed that all the data packets have been accumulated and that there is no error, the ML60852A returns an ACK packet to the host. At the same time, the receive packet ready bit of the corresponding EP status register will also be set and a request is sent to the local MCU in terms of an interrupt. Upon receiving this interrupt, the local MCU reads out the received data from the ML60852A and resets the receive packet ready bit.
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(6) Data packet transmission and reception procedure during isochronous transfer mode Transfer of data is the major function in the isochronous transfermode. When carrying out isochronous transfer between the ML60852A and the host, the following packet communications are carried out via the USB bus for the data transfer of each packet. (a) Token packet transfer (IN token or OUT token) from the host to the ML60852A. (b) Data packet transfer in the desired direction (from the host to the device or from the device to the host). In the isochronous transfer mode, there is no handshaking that reports whether or not the packet transfer was done normally. The ML60852A requests the local MCU to send or receive packet data by asserting the INTR pin. The interrupt cause is SOF. Upon receiving this interrupt, the local MCU writes the packet data into the transmit FIFO of the EP set for transmission (ISO IN) in the isochronous transfer mode, or reads out data from the receive FIFO of the EP set for reception (ISO OUT) in the isochronous transfer mode. The above procedures of transferring one packet of data are explained below for transmission and reception separately. 1) During transmission The EP for ISO IN has a two-layer FIFO configuration. One FIFO is used for storing the packet data that is written in by the MCU via the local bus. The other FIFO is used for transmitting the stored data to the USB bus when an IN token is received. The roles of the two FIFOs are interchanged when an SOF packet is received. Upon receiving an SOF interrupt, the local MCU writes the data to be transmitted during the next frame into the corresponding transmit FIFO of the EP of the ML60852A. When the host transmits an IN token packet, the ML60852A transmits to the host the packet data written in the transmit FIFO during the previous frame. 2) During reception The EP for ISO OUT has a two-layer FIFO configuration. One FIFO is used for storing the packet data that is output to the local bus when the MCU reads the received packet data. The other FIFO is used for storing the packet data received from the USB bus. The roles of the two FIFOs are interchanged when an SOF packet is received. Upon receiving an SOF interrupt, the local MCU reads out the data that has been received during the previous frame from the corresponding receive FIFO of the EP of the ML60852A. When the host transmits an OUT token and a data packet to the ML60852A, the ML60852A stores that received data packet in the receive FIFO, and that data packet is read out by the local MCU during the next frame.
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(7) Packets and Packet Sizes The ML60852A packs the transmit data into packets and unpacks (restores to the original form) the received data. The packed data that is recognized by the software client is a set of data consisting of one or more packets, and this is called an I/O request Packet (IRP). Among the several packets in an IRP, all the packets other than the last packet are transferred with the maximum packet size. Only the last packet can be transferred as a "short packet", that is, a packet whose size is less than the maximum packet size. I/O Request Packet (IRP)
Packet 1
Packet 2
Packet n-1
Packet
n
1 Packet M Bytes
Maximum packet size The ML60852A has payload registers corresponding to each end point, and it is possible to set the maximum packet size for each end point in these registers. The maximum packet size should be within the capacity of the corresponding FIFO, and can be set as follows: (1) EP0 Receive packet size can be 32 bytes or less; (2) EP0 Transmit packet size can be 32 bytes or less; (3) EP1 Transmit/receive packet size can be 64 bytes or less; (4) EP2 Transmit/receive packet size can be 64 bytes or less; (5) EP3 Transmit/receive packet size can be 32 bytes or less; (6) EP4 Bulk/interrupt transmit/receive packet size can be 64 bytes; In the 5EP mode, the EP4 isochronous packet size can be 512 bytes or less; In the 6EP mode, the EP4 isochronous packet size can be 256 bytes or less; (7) In the 6EP mode, the EP5 bulk/interrupt packet size can be 64 bytes or less; In the 6EP mode, the EP5 isochronous packet size can be 256 bytes or less. On the USB bus, the separation between successive packets is distinguished by appending a special signal condition called EOP (End of Packet) at the end of each packet. The appending of EOP during transmission and the detection and removal of EOP during reception are carried out by the ML60852A automatically. (1) At the time of transmission, the packet is deemed to have ended when the local MCU has completed writing the required number of bytes of data in the transmit FIFO and has then asserted the transmit ready status bit. (The actual addition of EOP is executed at the time of transmitting the data over the USB bus after waiting for the IN token from the host.) The packet will be a short packet if the transmit packet ready status bit is asserted after writing data with less number of bytes than the maximum packet size. In particular, by asserting the transmit packet ready status bit without writing any data, it is possible to form a null packet whose data length is zero.
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(2) At the time of reception, when an EOP is detected in the received data string, the ML60852A recognizes it as the end of the received packet and asserts the receive packet ready status bit. The number of bytes in the received packet is counted automatically by the receive byte count register (Note 1) corresponding to that end point. Note 1: Receive byte count register address: 58h to 5Dh and 74h to 75h. (8) Interrupts The ML60852A requests interrupts to the local MCU, etc., by asserting the -INTR pin. The interrupt causes are the following: (a) Setup ready for the 8-byte setup data (b) EP0 receive packet ready (c) EP0 transmit packet ready (d) EP1 transmit/receive packet ready (e) EP2 transmit/receive packet ready (f) EP3 transmit/receive packet ready (g) EP4 transmit/receive packet ready (h) EP5 transmit/receive packet ready (i) SOF (j) USB Bus reset assert (k) USB Bus reset de-assert (l) Suspend (m) Awake Although there is only one INTR pin, the local MCU can identify the contents of the interrupt by reading out the interrupt status register 1 (INTSTAT1) and the interrupt status register 2 (INTSTAT2). These interrupts can also be masked dynamically by making individual settings in the interrupt enable register 1 (INTENBL1) and the interrupt enable register 2 (INTENBL2). The causes of the interrupts, their setting and resetting conditions, and the responses to them are described below. The functions of the setup ready bit and the packet ready bit can, in some situations, be different from those described here because of some special automatic operations done by the ML60852A. Please see the descriptions of the registers EP0STAT to EP5STAT for more details of such functions. (1) Setup ready interrupt
Operation Setup ready interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) The setup ready bit (D2 of EP0STAT) is asserted when the 8-byte setup control data is received normally and has been stored in the set of setup registers. An interrupt is generated at this time if D0 of INTENBL1 has been asserted. The firmware can now read the set of setup registers. End of setup ready interrupt Local MCU (firmware) After making the firmware read the 8-byte setup data, write a "1" in bit D2 of EP0 status register (EP0STAT). This causes the interrupt to be de-asserted. The interrupt will not be de-asserted If a new 8-byte setup data is received during this period. In this case, discard the setup data that was being read at that time and read the new 8-byte setup data.
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(2) EP0 Receive packet ready interrupt This is used mainly during the reception of a data packet in a control write transfer.
Operation EP0 Receive packet ready interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) The EP0 receive packet ready bit (D0 of EP0STAT) is asserted during a control write transfer when the processing has changed from the setup stage to the data stage, and the ML60852A has detected EOP of the data packet and has stored the data without error in the EP0 receive FIFO. The end of a packet is recognized when an EOP has arrived in the cases of both full packets and short packets. An interrupt is generated at this time, if the EP0 receive packet ready interrupt enable bit (D6 of INTENBL1) has been asserted. (EOP: End of packet) End of EP0 receive packet ready interrupt Local MCU (firmware) In the case of EP0 reception, after the number of bytes of the EP0 receive FIFO data indicated by the EP0 receive byte count register (EP0RXCNT) has been read, write a "1" to the EP0 receive packet ready bit (bit D0 of EP0STAT). (This status is reset when a "1" is written in this bit.)
Note: A short packet is a packet with a number of bytes less than the maximum packet size.
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(3) EP0 Transmit packet ready interrupt This is used mainly during the transmission of a data packet in a control read transfer.
Operation EP0 Transmit packet ready interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) During a control read transfer when the processing has changed from Setup stage to Data stage, it is necessary for the local MCU (firmware) to write the data to be transmitted to the transmit FIFO of EP0. The local MCU must enable EP0 transmit packet ready interrupt bit (bit D7 of INTENBL1) to facilitate write operation to EP0TXFIFO. At this time, an EP0 transmit packet ready interrupt is generated. The cause of the interrupt is EP0 transmit packet ready bit (D1 of EP0STAT) being low. This interrupt will invoke the local MCU (firmware) to process EP0 transmit operation which will result in sending packets to the host. For the second and subsequent packets, in addition to EP0 transmit packet ready interrupt being enabled, before the interrupt is generated, it is necessary for an ACK response to come from the host for the packet that has just been sent. End of EP0 transmit packet ready interrupt Local MCU (firmware) In the case of EP0 transmission, after one packet of EP0 transmit data has been written in EP0TXFIFO, write a "1" into the EP0 transmit packet ready bit (bit D1 of EP0STAT). This puts the ML60852A in a state in which it can transmit the data (that is, it can transmit the data packet when an IN token arrives), and the INTR pin is de-asserted at the same time. Even when the number of bytes in the write data is less than the maximum packet size, it is possible to transmit the data by writing a "1" into the transmit packet ready status bit. This makes it possible to transmit a short packet.
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(4) Receive packet ready interrupts (EP1, EP2, EP3, EP4 bulk, EP5 bulk) These interrupts are generated when the respective EP has received an appropriate data packet from the USB bus and the local MCU can read that data.
Operation Receive packet ready interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) The receive packet ready bit (D0) of the corresponding EP status register (EPnSTAT) is asserted during data reception when the EOP of the data packet has been received and the data has been stored without error in the corresponding FIFO. The end of a packet is recognized when an EOP has arrived in the cases of both full packets and short packets. An interrupt is generated at this time, if the corresponding receive packet ready interrupt enable bit has been asserted. (EOP: End of packet) End of receive packet ready Local MCU (firmware) interrupt After the number of bytes in the receive FIFO data (EPnFIFO) indicated by the corresponding receive byte count register (EPnRXCNT) has been read, write a "1" into the receive packet ready bit D0 of the corresponding EP status register (EPnSTAT). (This status is reset when a "1" is written in this bit.)
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(5) Transmit packet ready interrupts (EP1, EP2, EP3, EP4 bulk, EP5 bulk) These interrupts are generated when it is possible for the local MCU to write the data packet to be sent to the USB bus from the corresponding EP.
Operation Transmit packet ready interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) (1) In the case of bulk transfer and interrupt transfer When the respective EP has been set for transmission (bit D7 of EPnCONF='1'), the transmit packet ready bit of the corresponding EP (bit D1 of EPnSTAT) is deasserted at which time it is possible to write the transmit data into the FIFO. At this time, an interrupt is generated if the corresponding EP transmit packet ready interrupt enable bit (INTENBL1) has been asserted. For the second and subsequent packets, in addition to this condition, before the interrupt is generated, it is necessary for an ACK response to come from the host for the packet that has just been sent. End of transmit packet ready Local MCU (firmware) interrupt (1) In the case of bulk transfer and interrupt transfer After the one packet of the corresponding EP transmit data has been written in EPnTXFIFO, write a "1" into the corresponding transmit packet ready bit (bit D1 of EPnSTAT). This puts the ML60852A in a state in which it can transmit the data and the INTR pin is de-asserted at the same time. When the number of bytes in the write data is less than the maximum packet size, a short packet can be sent by setting (write `1') the transmit packet ready status of the endpoint.
Note) EP1,EP2,EP4,and EP5 each has 2 layers of FIFO. Settings in the transmit packet ready control register (TXPKTCONT) control the assert and de-assert conditions of transmit pactet ready interrupts. For details, see"Transmit Packet Ready Control Register in INTERNAL REGISTERS.
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(6) SOF Interrupt
Operation SOF Interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) When SOF interrupt has been enalbed (bit D0 of INTENBL2), and an SOF packet is detected on the USB bus. When a "1" is written in the SOF interrupt status bit of the interrupt status register 2 (bit D2 of INTSTAT2).
End of SOF interrupt
Local MCU (firmware)
(7) USB Bus reset assert interrupt
Operation USB Bus reset assert interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) The ML60852A automatically detects the condition when the SE0 state continues for 2.5s or longer at the D+ and D- pins. Once this condition is detected, if USB bus reset assert interrupt has been enabled (D1 of INTENBL2) an interrupt is generated. Carry this out by firmware processing for bus reset. End of USB bus reset assert Local MCU (firmware) When a "1" is written in the corresponding bit of the interrupt status register 2 (D1 of INTSTAT2). interrupt
(8) USB Bus reset de-assert interrupt
Operation USB Bus reset de-assert interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) When USB Bus reset de-assert interrupt enable bit (D2 of INTENBL2) has been enalbed and there is a recovery to the J state from the SE0 state of 2.5s or longer at the D+ and D- pins. Carry this out by firmware processing for bus reset release. End of USB bus reset de-assert Local MCU (firmware) When a "1" is written in the corresponding bit of the interrupt status register 2 (D2 of INTSTAT2).
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(9) Suspend state interrupt
Operation Suspend state interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) When device suspend interrupt (D3 of INTENBL2) has been enabled and idle condition persists for 3ms or more at the D+ and D- pins. The internal oscillations in the ML60852A are stopped automatically when the idle condition continues for an additional 2ms after this interrupt has been generated. The firmware can take steps to put the device in the power save mode. End of suspend state interrupt Local MCU (firmware) When a "1" is written in the corresponding bit of the interrupt status register 2 (INTSTAT2).
(10) Awake interrupt
Operation Awake interrupt generation Source of operation ML60852A Description (conditions, responses, etc.) When device awake interrupt (D4 of INTENBL2) has been enabled and the EOP, which is the end of resume signal, is detected at the D+ and D- pins. When a "1" is written in the corresponding bit of the interrupt status register 2 (INTSTAT2).
End of awake interrupt
Local MCU (firmware)
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(9) DMA (Direct Memory Access) It is possible to carry out 8-bit wide or 16-bit wide DMA transfer for the bulk transfer of EP1, EP2, EP4, and EP5, and for the isochronous transfer of EP4 and EP5. The data bus used is the following: During 8-bit transfer: AD7 to AD0 During 16-bit transfer: D15 toD8, AD7 to AD0 It is possible to carry out DMA transfers over two channels, Channel 0 and Channel 1. Both demand transfer and single transfer are supported. The settings of the DMA transfer mode and parameters are done using the DMA control register and the DMA interval register described later in this manual. In the demand transfer mode, the DREQ pin is asserted when the reading or writing of a data packet becomes possible. The DREQ pin is de-asserted when the transfer of all the data of the receive packets is completed by the external DMA controller. Therefore, other devices cannot access the local bus during DMA transfer. On the other hand, in the single transfer mode, the DREQ pin is de-asserted at the end of transfer of the number of bytes (or words) of one transfer, and the other devices can access the local bus during this period. (10) Power-down When the ML60852A detects the suspend state on the USB bus, it automatically stops the internal oscillations and enters the power-down state. When the resume signal is detected on the USB bus, the oscillations are restarted automatically and the power-down state is released.
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(11) Operation of 2-layer FIFO structure during Bulk Transfer The FIFOs of EP1 and EP2 have a 64 bytes x 2-layer structure. Also, when EP4 is assigned for bulk transfer, its FIFO also has a 64-bytes x 2-layer structure. As a consequence, these FIFOs can temporarily store a maximum of 128 bytes of bulk transfer data. Please note that the double layered FIFO operation can be modified by changing the settings in the transmit packet ready control register (TXPKTCONT). (1) 2-Layer reception (bulk-out) operation ("O" indicates the assert (set to `1') condition and "x" indicates deassert (set to `0') condition)
Layer A PKT RDY x Layer B PKT RDY x x x x EPn receive PKT RDY x x INTR
In the case of 12345a6 In the case of 12345b6 1 2 3 4 5a Start storing data in layer A FIFO Data of one packet has been stored. Start reception and storing of data in layer B. Local MCU starts reading layer A. When the storing of packet in layer B is completed before the completion of reading layer A. When the reading of packet in layer A is completed before the completion of storing data in layer B. From 5a: Layer A has become empty. From 5b: Layer B has become full. Start reading layer B.
Layer A 64 bytes
Layer B 64 bytes
5b
x
x
x
x
6 7
x x
Note: The above illustration assumes that the local MCU (firmware) resets the receive packet ready bit of the respective EPnSTAT register immediately after completition of reading the received data in the corresponding endpoint's FIFO (EPnFIFO). * When one packet of receive data is stored in layer A of the FIFO and EOP is received, the ML60852A asserts the packet ready bit of EPn and also asserts the INTR pin. This makes it possible for the local MCU to read the receive data. * Subsequently, data can be received from the host, and the ML60852A switches the FIFO for storing to layer B. * When one packet of data described above has been read from layer A of the FIFO, make the local MCU reset the receive packet ready status of EPn (by writing a "1" into bit D0 of EPnSTAT). * At the time the EPn receive packet ready status is reset, if the reception of layer B has not been completed, the ML60852A resets the EPn receive packet ready status and de-asserts the INTR pin. * However, if the reception of layer B has been completed a the time the EPn receive packet ready status is reset, the ML60852A rejects the request from the local MCU to reset the EPn receive packet ready status, and continues to maintain the EPn receive packet ready status and the asserted condition of the INTR pin.
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(2) 2-Layer transmission (bulk-in) operation ("O" indicates the assert (set to `1') condition and "x" indicates deassert (set to `0') condition)
Layer A PKT RDY x x Layer B PKT RDY x x x x EPn transmit PKT RDY x x x x INTR
In the case of 12345a6 In the case of 12345b6 1 2 3 4 Layer A and layer B are both empty. The local MCU starts writing into layer A. Writing of one packet is completed. The data of layer A is being transmitted while the next packet is being written in layer B. When layer A is still being transmitted while the writing in layer B has already completed. When layer B is still being written while the writing in layer A has already completed. From 5a: Layer A has become empty. From 5b: Layer B has become full. Transmission of layer B is also started.
Layer A 64 bytes
Layer B 64 bytes
5a
x
5b
x
x
x
6 7
x x
x x
Note: The above illustration assumes that the local MCU (firmware) asserts (write `1') the transmit packet ready bit of the corresponding endpoint in register EPnSTAT immediately after completion of writing the transmit data into the corresponding EPnFIFO. * If the EPn transmit packet ready interrupt enable bit of INTENBL1 has been asserted, the transmit FIFO is empty, and EPn transmit packet ready bit is de-asserted, the EPn transmit packet ready interrupt is asserted. This makes it possible to write the transmit data into the EPn transmit FIFO. * When the data of one packet is written in layer A FIFO, make the local MCU set the transmit packet ready status (bit D1 of EPnSTAT). By setting the transmit packet ready status, it becomes possible to transmit data to the host. At this time, since layer B is still empty, the INTR pin maintains the asserted condition, thereby indicating that the next packet data can be written. In this case, although bit D1 of EPnSTAT remains in the '0' condition, the ML60852A recognizes that transmission is possible from layer A and starts transmission when an IN token is received from the host. * It is possible for the local MCU to write the next packet of transmit data in the layer B FIFO while the data in layer A is being transmitted over the USB bus. * When the writing of the data to be transmitted in layer B has been completed, the local MCU sets the transmit packet ready bit, and the INTR pin becomes de-asserted at this time if the transmission of layer A data has not been completed (that is, the ACK message is received from the host and the transmit packet ready bit is reset). The local MCU cannot yet write the subsequent packet. * If the layer A becomes empty before layer B goes into the transmit enable condition and transmission from layer A FIFO is carried out normally, an ACK is received from the host in response to this succussful transmission. This ACK will cause ML60852A to automatically deassert the layer A packet ready bit and hence generate an interrupt cause. The INTR pin remains asserted, and the local MCU can write data into layer A FIFO after completion of writing into layer B FIFO. * The transmission of data in layer A is continued from state, and when layer A becomes empty and the transmission is completed normally, an ACK response is received from the host, whereupon the ML60852A asserts the INTR pin thereby prompting the local MCU to write data into layer A.
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(12) Error Processing and Retry Operation 1) Error processing during transmission When an error such as a CRC error is detected in the data transmitted by the ML60852A, the host will not send the ACK packet, and hence the ML60852A does not reset the transmit packet ready status, but waits while retaining the current packet of data. The current packet of data is transmitted again when the next IN token is received from the host. 2) Error processing during reception When an error is detected in the data received over the USB bus, the ML60852A does not assert the interrupt signal to the local MCU and will also not send any message to the host (leading to a timeout condition). When the timeout condition is generated, the host recognizes that an error has occurred, and can take measures such as re-transmitting the data, etc. In addition, since no interrupt request is generated, the local MCU will not read the erroneous data.
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INTERNAL REGISTERS
The register file of the ML60852A includes registers to set operating conditions and registers to report the status of operating and the results of processing. These registers are read only, write only or capable of boh read and write. The setup register where setup data transmitted from host to device in a control pipe are stored is mapped in this register file. Also, data that are tranmitted or received by the device are transferred using transmit and receive FIFOs mapped in the addresses of the register file. The mapping of these registers are described in the following pages.
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Address and Names of Registers (1)
Category Address 70h 78h 79h 7Ah FIFO 7Bh 7Ch 7Dh Symbol EP0TXFIFO EP0RXFIFO EP1FIFO EP2FIFO EP3FIFO EP4FIFO EP5FIFO R/W W R R or W R or W R or W R or W R or W Register name EP0 Transmit FIFO EP0 Receive FIFO EP1 Transmit/Receive FIFO EP2 Transmit/Receive FIFO EP3 Transmit/Receive FIFO EP4 Transmit/Receive FIFO EP5 Transmit/Receive FIFO Page 34 34 35 35 36 36 37
00h 01h 02h 03h 04h 05h 06h 07h 20h 21h Common 22h 24h 25h 2Dh 2Eh 2Fh 30h
bmRequestType bRequest wValueLSB wValueMSB wIndexLSB wIndexMSB wLengthLSB wLengthMSB DVCADR INTSTAT1 INTSTAT2 INTENBL1 INTENBL2 FRAMELSB FRAMEMSB SYSCON POLSEL
R R R R R R R R R/W R/Rst R/Rst R/W R/W R R R/W R/W
bRequest Type Setup Register bRequest Setup Register wValueLSB Setup Register wValueMSB Setup Register wIndexLSB Setup Register wIndexMSB Setup Register wLengthLSB Setup Register wLengthMSB Setup Register Device Address Register Interrupt Status Register 1 Interrupt Status Register 2 Interrupt Enable Register 1 Interrupt Enable Register 2 Frame Number LSB Register Frame Number MSB Register System Control Register Polarity Selection Register
38 38 39 39 40 40 41 41 44 45 46 47 48 49 49 50 50
10h 11h DMA 12h 13h
DMA0CON DMA0INTVL DMA1CON DMA1INTVL
R/W R/W R/W R/W
DMA0 Control Register DMA0 Interval Register DMA1 Control Register DMA1 Interval Register
42 43 42 43
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Address and Names of Registers (2)
Category Address 40h 41h 42h 43h 44h 45h Symbol EP0CONF EP1CONF EP2CONF EP3CONF EP4CONF EP5CONF R/W R/W R/W R/W R/W R/W R/W Register name EP0 Configuration Register EP1 Configuration Register EP2 Configuration Register EP3 Configuration Register EP4 Configuration Register EP5 Configuration Register Page 52 53 53 53 53 53
48h 49h 4Ah 4Bh 4Ch 4Dh
EP0CONT EP1CONT EP2CONT EP3CONT EP4CONT EP5CONT
R/W R/W R/W R/W R/W R/W
EP0 Control Register EP1 Control Register EP2 Control Register EP3 Control Register EP4 Control Register EP5 Control Register
54 55 55 55 55 55
EP Support
50h 51h 52h 53h 54h 55h
EP0PLD EP1PLD EP2PLD EP3PLD EP4PLDLSB EP5PLDLSB
R/W R/W R/W R/W R/W R/W
EP0 Payload Register EP1 Payload Register EP2 Payload Register EP3 Payload Register EP4 Payload LSB Register EP5 Payload LSB Register
56 56 56 57 57 57
58h 59h 5Ah 5Bh 5Ch 5Dh
EP0RXCNT EP1RXCNT EP2RXCNT EP3RXCNT EP4RXCNTLSB EP5RXCNTLSB
R R R R R R
EP0 Receive Byte Counter Register EP1 Receive Byte Counter Register EP2 Receive Byte Counter Register EP3 Receive Byte Counter Register EP4 Receive Byte Counter LSB Register EP5 Receive Byte Counter LSB Register
58 58 58 59 59 59
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Address and Names of Registers (3)
Category Address 60h 61h 62h 63h 64h 65h Symbol EP0STAT EP1STAT EP2STAT EP3STAT EP4STAT EP5STAT R/W Register name EP0 Status Register EP1 Status Register EP2 Status Register EP3 Status Register EP4 Status Register EP5 Status Register Page 60 63 63 64 63 63
EP Support
6Ch 6Dh
EP4PLDMSB EP5PLDMSB
R/W R/W
EP4 Payload MSB Register EP5 Payload MSB Register
65 65
74h 75h
EP4RXCNTMSB EP5RXCNTMSB
R R
EP4 Receive Byte Counter MSB Register EP5 Receive Byte Counter MSB Register
66 66
3Eh
TXPKTCONT
R/W
Transmit Packet Ready Control Register
67
Option
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FUNCTIONS OF REGISTERS
EP0 Transmit FIFO (EP0TXFIFO)
Address Type Access type D7 After a hardware reset After a bus reset Definition x x D6 x x D5 x x D4 x x D3 x x D2 x x D1 x x D0 x x 0 x 70 Byte data Write only
EP0 Transmit data
The EP0 transmit data can be written in by writing to the address 70h. The transmit data to the host in the data stage during a control read transfer is stored in EP0TXFIFO. When the ML60852A issues an EP0 transmit packet ready interrupt request, the local MCU writes the transmit data to the address 70h. It is possible to write the packet data successively by writing continuously. The EP0TXFIFO is cleared under the following conditions. 1. When an ACK signal is received from the host for the data transmission from EP0 2. When a setup packet is received EP0 Receive FIFO (EP0RXFIFO)
Address Type Access type D7 After a hardware reset After a bus reset Definition x x D6 x x D5 x x D4 x x D3 x x D2 x x D1 x x D0 x x 0 x 78 Byte data Read only
EP0 Receive data
The receive data from the host computer in the data sate during a control Write transfer is stored in EP0RXFIFO. EP0 receive data can be read out by the local MCU through reading the address 78h when the ML60852A issues an EP0 receive packet ready interrupt request. It is possible to read successively the data in the packet by reading continuously. The EP0RXFIFO is cleared under the following conditions: 1. When the local MCU resets EP0 receive packet ready bit. 2. When a setup packet is received. 3. When the local MCU writes a "0" in the stall bit.
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EP1 FIFO (EP1FIFO)
Address Type Access type 0 x 79 Byte data Write only or Read only D7 After a hardware reset After a bus reset Definition x x D6 x x D5 x x D4 x x D3 x x D2 x x D1 x x D0 x x
EP1 Transmit data or EP1 receive data
It is possible to specify the direction of transfer of EP1 by setting the EP1 configuration register EP1CONF. The FIFO address of EP1 is the same in both the transmit direction and the receive direction. When EP1CONF (D7) = 0, EP1 is in the receive direction and EP1FIFO is in the read-only state. When EP1CONF (D7) = 1, EP1 is in the transmit direction and EP1FIFO is in the write-only state. When set for transmission, all bytes of EP1FIFO can be cleared by clearing EP1FIFO (writing a "1" into EP1CONT (D2)). EP2 FIFO (EP2FIFO)
Address Type Access type 0 x 7A Byte data Write only or Read only D7 After a hardware reset After a bus reset Definition x x D6 x x D5 x x D4 x x D3 x x D2 x x D1 x x D0 x x
EP2 Transmit data or EP2 receive data
It is possible to specify the direction of transfer of EP2 by setting the EP2 configuration register EP2CONF. The FIFO address of EP2 is the same in both the transmit direction and the receive direction. When EP2CONF (D7) = 0, EP2 is in the receive direction and EP2FIFO is in the read-only state. When EP2CONF (D7) = 1, EP2 is in the transmit direction and EP2FIFO is in the write-only state. When set for transmission, all bytes of EP2FIFO can be cleared by clearing EP2FIFO (writing a "1" into EP2CONT (D2)).
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EP3 FIFO (EP3FIFO)
Address Type Access type 0 x 7B Byte data Write only or Read only D7 After a hardware reset After a bus reset Definition x x D6 x x D5 x x D4 x x D3 x x D2 x x D1 x x D0 x x
EP3 Transmit data or EP3 receive data
It is possible to specify the direction of transfer of EP3 by setting the EP3 configuration register EP3CONF. The FIFO address of EP3 is the same in both the transmit direction and the receive direction. When EP3CONF (D7) = 0, EP3 is in the receive direction and EP3FIFO is in the read-only state. When EP3CONF (D7) = 1, EP3 is in the transmit direction and EP3FIFO is in the write-only state. When set for transmission, all bytes of EP3FIFO can be cleared by clearing EP3FIFO (writing a "1" into EP3CONT (D2)). EP4 FIFO (EP4FIFO)
Address Type Access type 0 x 7C Byte data Write only or Read only D7 After a hardware reset After a bus reset Definition x x D6 x x D5 x x D4 x x D3 x x D2 x x D1 x x D0 x x
EP4 Transmit data or EP4 receive data
It is possible to specify the direction of transfer of EP4 by setting the EP4 configuration register EP4CONF. The FIFO address of EP4 is the same in both the transmit direction and the receive direction. When EP4CONF (D7) = 0, EP4 is in the receive direction and EP4FIFO is in the read-only state. When EP4CONF (D7) = 1, EP4 is in the transmit direction and EP4FIFO is in the write-only state. When set for transmission, all bytes of EP4FIFO can be cleared by clearing EP4FIFO (writing a "1" into EP4CONT (D2)).
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EP5 FIFO (EP5FIFO)
Address Type Access type 0 x 7D Byte data Write only or Read only D7 After a hardware reset After a bus reset Definition x x D6 x x D5 x x D4 x x D3 x x D2 x x D1 x x D0 x x
EP5 Transmit data or EP5 receive data
In the ML60852A, by making a setting of the system control register, it is possible to select either the 5EP mode with the number of EPs being 5 or the 6EP mode with the number of EPs being 6. In the 5EP mode, only EP0 to EP4 are present and EP5 will not be present. In the EP6 mode, all end points EP0 to EP5 will be valid. It is possible to specify the direction of transfer of EP5 by setting the EP5 configuration register EP5CONF. The FIFO address of EP5 is the same in both the transmit direction and the receive direction. When EP5CONF (D7) = 0, EP5 is in the receive direction and EP5FIFO is in the read-only state. When EP5CONF (D7) = 1, EP5 is in the transmit direction and EP5FIFO is in the write-only state. When set for transmission, all bytes of EP5FIFO can be cleared by clearing EP5FIFO (writing a "1" into EP5CONT (D2)).
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bmRequestType Setup Register (bmRequestType)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 Type D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 00 Bit map Read only
Receiving side definitions 0 = Device 1 = Interface 2 = End point 3 = Others 4 to 31 = Reserved 0 = Standard 1 = Class 2 = Vendor 3 = Reserved Data transfer direction 0 = From the host to the device 1 = From the device to the host
During the setup stage of control transfer based on a request from the host, the 8-byte setup data transmitted by the host is automatically received by the ML60852A and is stored in the 8 setup registers including this register. The formats of these data items are defined in Section 9.3 of the USB Standards. bRequest Setup Register (bRequest)
Address Type Access type D7 After a hardware reset After a bus reset Definition x x D6 x x D5 x x D4 x x D3 x x D2 x x D1 x x D0 x x 0 x 01 Byte data Read only
Request code
During the setup stage of control transfer based on a request from the host, the 8-byte setup data transmitted by the host is automatically received by the ML60852A and the second byte is stored in this register. The content of the request code is defined in Section 9.3 of the USB Standards and in related documents.
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wValueLSB Setup Register (wValueLSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 02 2-Byte data Read only
wValueLSB
During the setup stage of control transfer based on a request from the host, the 8-byte setup data transmitted by the host is automatically received by the ML60852A and the third byte is stored in this register. This is the lower-order byte of the two-byte data. wValueMSB Setup Register (wValueMSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 03 2-Byte data Read only
wValueMSB
During the setup stage of control transfer based on a request from the host, the 8-byte setup data transmitted by the host is automatically received by the ML60852A and the fourth byte is stored in this register. This is the higherorder byte of the two-byte data.
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wIndexLSB Setup Register (wIndexLSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 04 2-Byte data Read only
wIndexLSB
During the setup stage of control transfer based on a request from the host, the 8-byte setup data transmitted by the host is automatically received by the ML60852A and the fifth byte is stored in this register. This is the lower-order byte of the two-byte data. wIndexMSB Setup Register (wIndexMSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 05 2-Byte data Read only
wIndexMSB
During the setup stage of control transfer based on a request from the host, the 8-byte setup data transmitted by the host is automatically received by the ML60852A and the sixth byte is stored in this register. This is the higher-order byte of the two-byte data.
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wLengthLSB Setup Register (wLengthLSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 06 2-Byte data Read only
wLengthLS
During the setup stage of control transfer based on a request from the host, the 8-byte setup data transmitted by the host is automatically received by the ML60852A and the seventh byte is stored in this register. This is the lowerorder byte of the two-byte data. wLengthMSB Setup Register (wLengthMSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 07 2-Byte data Read only
wLengthMSB
During the setup stage of control transfer based on a request from the host, the 8-byte setup data transmitted by the host is automatically received by the ML60852A and the eighth byte is stored in this register. This is the higherorder byte of the two-byte data.
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DMA0, 1 Control Registers (DMA0, 1CON)
Address Type Access type D7 After a hardware reset After a bus reset Definition DMA Enable 0 = DMA Disabled 1=DMA Enabled DMA Address mode 0 = Single address mode 1 = Dual address mode DMA Byte count 0 = The number of bytes is not inserted 1 = The data of the number of bytes is inserted in the leading byte or leading word of the transfer data. (Note 1) DMA Transfer data width 0 = Byte width (8 bits) 1 = Word width (16 bits) (Note 2) DMA Transfer mode 0=Single transfer mode 1=Demand transfer mode EP Specification Specifies the target EP for the DMA transfer 0=EP1, 1=Ep2, 2=EP4, 3=EP5 (Note 3) DMA Interrupting (Note 4) 0=Normal operation 1=The DREQ pin is de-asserted 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 0 x 10, 0 x 12 Bit map Read/Write
The previous value is retained
Note 1: During the 16-bit mode, the higher order byte of the leading word will be 00h. Note 2: The higher order byte and the lower order byte are allocated in the little-endian sequence. That is, the LSB corresponds to AD0 to AD7 and the MSB corresponds to D8 to D15. During the 16-bit mode and when the packet size is an odd number of bytes, the higher order byte of the last word will be 00h. Note 3: When the EP specifications for the DMA channels 0 and 1 both have the same values, DREQ0, DREQ 1 and DACK0, DACK 1 will respectively be equivalent. Note 4: The settings of all bits other than bit D7, that is, of bits D0 to D6 should be completed at the time of initialization (at the latest, before a token packet for EP1 to Ep5 arrives), and should not be altered thereafter. Write a "1" to D7 in order to temporarily stop DMA transfer in the middle. When the transfer is restarted by writing a "0" to D7, it is possible to restart the transfer from the byte (or word) next to the one at which the transfer was interrupted.
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DMA0, 1 Interval Registers (DMA0, 1INTVL)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 0 x 11, 0 x 13 Byte data Read/Write
The previous value is retained Interval time
This specifies the interval in the single DMA transfer mode, that is, the time duration after the end of DMA transfer of the previous byte (or the previous word) until DREQ is asserted again. The time for 1 bit is 84ns (12 MHz, period of one-cycle). Interval time = (DREQ enable time) + 84xn (ns) See the description of the DMA Transfer Timings (1), (2), (5), and (6) for the DREQ enable time.
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Device Address Register (DVCADR)
Address Type Access type D7 After a hardware reset After a bus reset Definition Device address (R/W) 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 0 x 20 7-bit data Read/Write
The device address given by a SET_ADDRESS request from the host is written in this register by the local MCU. Thereafter, the ML60852A judges the specified address in the token from the host, and this device will process only the token packets sent to this device address. Bit D7 is fixed at "0", and even if a "1" is written, it will be ignored.
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Interrupt Status Register 1 (INTSTAT1)
Address Type Access type D7 After a hardware reset After a bus reset Definition Setup ready interrupt status (stup_ry) EP1 packet ready interrupt status (ep1_pry) EP2 packet ready interrupt status (ep2_pry) EP3 packet ready interrupt status (ep3_pry) EP4 packet ready interrupt status (ep4_pry) (Note) EP5 packet ready interrupt status (ep5_pry) (Note) EP0 receive packet ready interrupt status EP0 transmit packet ready interrupt status 0 X D6 0 x D5 0 x D4 0 x D3 0 x D2 0 x D1 0 x D0 0 0 0 x 21 Bit map Read only
Note: When isochronous transfer has been set in the EP4 or EP5 configuration register, the EP4 or EP5 packet ready interrupt status will always be fixed at "0".
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Interrupt Status Register 2 (INTSTAT2)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 0 SOF Interrupt status (sof) USB Bus reset assert interrupt status (busrst_ass) USB Bus reset de-assert interrupt status (busrst_des) D4 0 0 D3 0 0 D2 0 note D1 0 D0 0 0 0 x 22 Bit map Read/Reset
note ; The previous value is retained
Device suspend state interrupt status (suspend) Device awake state interrupt status (awake)
The status bit becomes "1" when the corresponding interrupt is generated. The status is cleared when a "1" is written in that status bit itself. (See Section (8) "Interrupt" for Functional Descriptions.)
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Interrupt Enable Register 1 (INTENBL1)
Address Type Access type D7 After a hardware reset After a bus reset Definition Setup ready interrupt enable (stup_ry) EP1 packet ready interrupt enable (ep1_pry) EP2 packet ready interrupt enable (ep2_pry) EP3 packet ready interrupt enable (ep3_pry) EP4 packet ready interrupt enable (ep4_pry) EP5 packet ready interrupt enable (ep5_pry) EP0 receive packet ready interrupt enable (ep0rx_pry) EP0 transmit packet ready interrupt enable (ep0tx_pry) 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 0 x 24 Bit map Read/Write
The previous value is retained
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Interrupt Enable Register 2 (INTENBL2)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 D5 0 0 SOF Interrupt enable (sof) USB Bus reset assert interrupt enable (busrst_ass) USB Bus reset de-assert interrupt enable (busrst_des) D4 0 D3 0 D2 0 D1 0 D0 0 0 x 25 Bit map Read/Write
The previous value is retained
Device suspend state interrupt enable (suspend) Device awake state interrupt enable (awake)
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Frame Number LSB Register (FRAMELSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 2D 11-Bit data Read only
Frame number LSB
This is valid when containing an end point in the isochronous transfer mode. When a start of frame (SOF) packet is transmitted by the host, the ML60852A automatically writes into the FRAMELSB and FRAMEMSB registers. Frame Number MSB (FRAMEMSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 2E 11-Bit data Read only
Frame number MSB
This is valid when containing an end point in the isochronous transfer mode. When a start of frame (SOF) packet is transmitted by the host, the ML60852A automatically writes into the FRAMELSB and FRAMEMSB registers.
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System Control Register (SYSCON)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 Software reset (R/W) (sereset) Power-down mode (R/W) (power) 0 = Power saving is not done in the suspend mode. 1 = Power saving is done in the suspend mode. EP Mode (R/W) (ep_mod) 0 = EP0 to EP5 1 = EP0 to EP4 Pull-up control (R/W) (plup) Remote wakeup (R/W) PLL Enable (pll_enable) PLL Multiplication factor selection (fsel) 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 0 x 2F Bit map Read/Write
The previous value is retained
Write-only bit. Even when this bit is read out, it will be fixed at "0". A system reset is executed when a "1" is written in this bit. This is functionally equivalent to a hardware reset. However, this bit itself will always remain "0". Power-down mode: Read/Write bit. When this bit is "0", the oscillations will not be stopped even during the suspend mode. When this bit is made "1"', the oscillations will be stopped in the suspend mode and the device goes into the power save mode. EP mode: Read/Write bit. The 6EP mode is selected when this bit is 0 and the 5EP mode is selected when this bit is "1". Pull-up control: The content of this bit becomes valid when the ADSEL pin is "L". When the ADSEL pin is "L", the internal switch becomes ON and the ALE pin is pulled up to the Vcc level if this bit is "1". On the other hand, if the ADSEL pin is "L" and also this bit is "0", the internal switch is made OFF and the ALE pin goes into the high impedance state. Remote wakeup: A remote wakeup is executed when a "1" is written in this bit. However, this bit itself will always remain "0". PLL enable: This bit is for enabling the internal PLL. The internal PLL cannot be used when this bit is "0". The signal input to the XIN pin becomes the source oscillations for the internal circuits. The internal PLL can be used when this bit is "1". PLL multiplication factor selection: The frequency multiplication factor is 4 when this bit is "0", and will be 8 when this bit is "1". (The source oscillator frequency will be 12 MHz in the 4x mode and will be 6 MHz in the 8x mode.)
Software reset:
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Polarity Selection Register (POLSEL)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 D5 0 0 DREQ0 polarity 0 = Active Low 1 = Active High DACK0 polarity 0 = Active High 1 = Active Low DREQ1 polarity 0 = Active Low 1 = Active High DACK1 polarity 0 = Active High 1 = Active Low INTR polarity 0 = Active Low 1 = Active High D4 0 D3 0 D2 0 D1 0 D0 0 0 x 30 Bit map Read/Write
The previous value is retained
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EP0 Configuration Register (EP0CONF)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 1 D3 0 0 0 D2 0 0 0 D1 0 0 0 D0 0 0 0 Transfer type (read only) 00 = Control transfer Configuration bit (read only) 0 x 40 Bit map Read only
Transfer type:
Configuration bit:
Although these bits indicate the type of transfer, since EP0 has been fixed for control transfer in the ML60852A, this value is always fixed at 00h. The local MCU cannot write into these bits. The configuration bit of EP0 becomes "1" after a USB bus reset. When this bit is "1", the data transmitted by the host to the end point can be received and also data can be transmitted from the end point to the host. When this bit is "0", this LSI will not respond to any transaction targeting this end point. This bit cannot be written in by the local MCU.
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EP1, 2, 3, 4, 5 Configuration Registers (EP1, 2, 3, 4, 5CONF)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 0 D5 0 0 0 D4 0 1 D3 0 0 0 D2 0 0 0 Transfer type 10 = Bulk transfer 11 = Interrupt transfer 01 = Isochronous transfer Configuration bit Transfer direction 0=Reception, 1=transmission D1 0 0 D0 0 0 0 x 41 to 45 Bit map Read only
Transfer type: Configuration bit:
Transfer direction:
These bits indicate the type of transfer. Only EP4 and EP5 can be set to isochronous transfer. When a Set Configuration request to make that EP active is received from the host, make sure that the local MCU writes a "1" into this bit during the status stage in the control transfermode. Data transmission and reception can be made between the host and the EP when this bit is "1". When this bit is "0", this LSI will not respond to the transactions targeted at that EP. The local MCU sets the direction of data transfer using this bit.
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EP0 Control Register (EP0CONT)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 0 D4 x x D3 0 0 0 D2 0 0 0 Stall bit (R/W) Data sequence toggle bit (reception) Data sequence toggle bit (transmission) D1 x x D0 0 0 0 x 48 Bit map Read/Write
During EP0 reception (data stage of a control write transfer), if a packet with a number of bytes exceeding the maximum packet size specified in EP0PLD is received (or if the EOP packet is missing), the ML60852A automatically sets this bit to "1". In order to conform to the Protocol Stall of USB Rev. 1.1, this bit is reset automatically to "0" when a setup packet is received. Data sequence toggle bits: The ML60852A automatically carries out synchronization using the data sequence toggle mechanism. Further, any write operation to these bits (D4 and D1) will be invalid.
Stall bit:
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EP1, 2, 3, 4, 5 Control Registers (EP1, 2, 3, 4, 5CONT)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 Stall bit (R/W) Data sequence toggle bit (R/Reset) FIFO Clear (R/Reset) Rate feedback (R/W) D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 49 to 4D Bit map See below
During EP0 reception (data stage of a control write transfer), if a packet with a number of bytes exceeding the maximum packet size specified in EP0PLD is received (or if the EOP packet is missing), the ML60852A automatically sets this bit to "1". Data sequence toggle bit: A reset will be made when a "1" is written in this bit. At the time of initializing the EP, reset the toggle bit of the data packet by writing a "1" to this bit, and specify PID of DATA0 (this bit too will become "0"). Thereafter, the synchronization operation using the data sequence toggle mechanism will be made automatically. FIFO Clear: The EP will be valid only when it has been set for transmission by the EP control register. When a "1" is written in this bit, the transmit FIFO of that EP will be cleared. (However, this bit itself will remain "0".) Rate feedback: This bit is valid only in the case of EP3. This bit will be fixed at "0" in all other EPs.
Stall bit:
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EP0 Payload Register (EP0PLD)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 1 1 1 D4 0 0 0 Maximum packet size D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 50 6-Bit data Read only
Maximum packet size: Since the FIFO of EP0 in the ML60852A has a size of 32 bytes, write 20h into the byte bMaxPacketSize0 of the device descriptor. The maximum packet size is fixed at 32 bytes in this EP0PLD register. When a packet with more than 32 bytes is received, the stall bit in the EP0 status register is asserted and the stall handshake is returned to the host. EP1, 2 Payload Registers (EP1, 2PLD)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 51, 52 7-Bit data Read/Write
Maximum packet size (R/W)
Maximum packet size: Make the local MCU write in this register the value of the descriptor wMaxPacketSize of the end point selected by the Set_Configuration request from the host. The size of all packets other than a short packet is specified here in units of a byte. When the EP has been assigned for reception, if a data packet with a number of bytes exceeding the maximum packet size specified in this register is received, the receive packet ready status bit is not asserted, but the stall bit is set in EOP and the stall handshake is returned to the host. On the other hand, when the EP has been assigned for transmission, the transmit packet ready bit is set automatically when writing by the DMA controller of data with the maximum packet size specified in this register is completed. The content of this register is ignored during non-DMA transmission of data.
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EP3 Payload Register (EP3PLD)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 Maximum packet size (R/W) D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 53 6-Bit data Read/Write
Maximum packet size: Make the local MCU write in this register the value of the descriptor wMaxPacketSize of the end point selected by the Set_Configuration request from the host. The size of all packets other than a short packet is specified here in units of a byte. Set 20h (32 bytes) or less because the FIFO size is 32 bytes. When EP3 has been assigned for reception, if a data packet with a number of bytes exceeding the maximum packet size specified in this register is received, the receive packet ready status bit is not asserted, but the stall bit is set in EOP and the stall handshake is returned to the host. There is no need to use this register when EP3 has been assigned for transmission. EP4, 5 Payload LSB Registers (EP4, 5PLDLSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 54, 55 10-Bit or 9-bit data Read/Write
Maximum packet size LSB (R/W)
Maximum packet size LSB: Make the local MCU write in this register the value of the descriptor wMaxPacketSize of the end point selected by the Set_Configuration request from the host. The lower 8 bits should be stored in this register and the higher-order bytes should be written in the EP4,5 payload registers MSB. The maximum packet size is specified in units of a byte. When the EP has been assigned for reception, if a data packet with a number of bytes exceeding the maximum packet size specified in these registers is received, the receive packet ready status bit is not asserted, but the stall bit is set in EOP and the stall handshake is returned to the host. On the other hand, when the EP has been assigned for transmission, the transmit packet ready bit is set automatically when writing by the DMA controller of data with the maximum packet size specified in this register is completed.
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EP0 Receive Byte Counter Register (EP0RXCNT)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 58 6-Bit data Read only
Receive byte count (R)
The ML60852A automatically counts the number of bytes in the packet being received. Although the counting is done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value and reads out the data of one packet from the EP0 Receive FIFO. The EP0RXCNT register is cleared under the following conditions. 1. When the local MCU resets the EP receive packet ready bit. 2. When a setup packet is received. 3. When the local MCU writes a "0" into the stall bit. EP1, 2 Receive Byte Counter Registers (EP1, 2RXCNT)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 59, 5A 7-Bit data Read only
Receive byte count (R)
The ML60852A automatically counts the number of bytes in the packet being received. Although the counting is done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value and reads out the data of one packet from the EP1/2 Receive FIFO. This register will be invalid when the transfer direction of the EP is set for transmission. The EP1,2RXCNT register is cleared under the following conditions. 1. When an OUT token is received for the EP. 2. When the local MCU resets the EP receive packet ready bit. 3. When the local MCU writes a "0" into the stall bit.
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EP3 Receive Byte Counter Register (EP3RXCNT)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 5B 6-Bit data Read only
Receive byte count (R)
The ML60852A automatically counts the number of bytes in the packet being received. Although the counting is done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value and reads out the data of one packet from the EP3 Receive FIFO. This register will be invalid when the transfer direction of the EP is set for transmission. The EP3RXCNT register is cleared under the following conditions. 1. When an OUT token is received for EP3. 2. When the local MCU resets the EP receive packet ready bit. 3. When the local MCU writes a "0" into the stall bit. EP4, 5 Receive Byte LSB Counter Registers (EP4, 5RXCNTLSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 0 x 5C, 5D 10-Bit or 9-bit data Read only
Receive byte count LSB (R)
The ML60852A automatically counts the number of bytes in the packet being received. Although the counting is done only up to the number of bytes equal to the maximum packet size specified in the payload register in the case of a full packet, the count will be less than that size in the case of a short packet. The local MCU refers to this value and reads out the data of one packet from the EP4/5 Receive FIFO. The lower 8 bits of the receive byte count are stored in this register and the higher order bits are stored in the EP receive byte counter MSB. This register will be invalid when the transfer direction of the EP is set for transmission. The EP4,5RXCNT register is cleared under the following conditions. 1. When an OUT token is received for the EP. 2. When the local MCU resets the EP receive packet ready bit. 3. When the local MCU writes a "0" into the stall bit.
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EP0 Status Register (EP0STAT)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 D4 0 0 D3 0 0 0 EP0 receive packet ready (R/Reset) EP0 transmit packet ready (R/Set) Setup ready (R/Reset) EP0 stage (R) 00 = Default state 01 = Data stage 10 = Data stage completed state D2 0 0 D1 0 0 D0 0 0 0 x 60 Bit map See below
Please note the R/Reset and R/Set notation used above. R/Reset means: the bit field can be read by the local MCU/and it is Reset (to `0') when a "1" is written to it. The R/Set means: the bit field can be read by the local MCU/and it is Set (to `1') when a 1 is written to it. Setup ready: This bit is set automatically when a setup packet normally arrives in the 8-byte setup register, and the EP0 Receive FIFO is locked. If INTENBL1(0) is asserted, the INTR pin is also asserted automatically when this bit is set. The local MCU should write a "1" into this bit after reading out the 8-byte setup data. When this is performed, the setup ready bit is reset and the INTR pin also is de-asserted. During a control write transfer, the packet ready bit of EP0 is reset simultaneously and the lock condition is released, and it becomes possible to receive packets by EP0 during the data stage. The register will not change even if a "0" is written in this bit.
EP0 transmit packet ready bit (D1): The local MCU can read this bit. Writing when D1=1 sets this bit to "1". The asserting and de-asserting conditions are described below.
Bit name EP0 transmit packet ready (D1) Bit name EP0 transmit packet ready (D1) Asserting condition When the local MCU has set this bit De-asserting condition 1. When an ACK is received from the host for data transmission 2. When a setup packet is received Operation when asserted Data can be transmitted from EP0. Operation when de-asserted EP0 is locked. That is, an NAK is automatically returned when an IN token is sent from the host.
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EP0 receive packet ready bit (D0): The local MCU can read this bit. Writing a "1" when D0=1 resets this bit to "0". The asserting and de-asserting conditions are described below.
Bit name EP0 receive packet ready (D0) Asserting condition 1. When data is received by EP0 and stored in FIFO 2. When a setup packet is received during control Read transfer or control Write transfer Bit name EP0 receive packet ready (D0) De-asserting condition 1. When the local MCU has reset this bit ( a "1" is written in this bit) 2. When the local MCU resets the setup ready bit during control Write transfer Operation when asserted EP0 is locked (an NAK is automatically returned when a data packet is received from the host). Data can be read from EP0RXFIFO by local MCU. Operation when de-asserted EP0 can receive data.
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EP0 Stage (D5, D4): These bits indicate the stage transition during control transfer. The flowchart of the stage transition is shown below.
Hardware Reset USB Bus Reset
Default State
Condition 1
Data State
Condition 2
Condition 3 Condition 1 Data Stage Completed State
Condition 1: Condition 2: Condition 3:
Reception of a setup packet of control READ transfer or control WRITE transfer. Reception of a setup packet of control transfer without data. Reception of a token (IN/OUT) of a direction opposite to the data flow in the data stage.
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EP1, 2, 4, 5 Status Registers (EP1, 2, 4, 5STAT)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 EP Receive packet ready (Read/Reset) EP Transmit packet ready (Read/Set) D1 0 0 D0 0 0 0 x 61, 62, 64, 65 Bit map See below
This register is valid only when the corresponding EP has been set for bulk or interrupt transfer. EP1,2,4,5 Receive packet ready bit (D0): This bit can be read by the local MCU. Also, this bit can be made "0" by writing a "1" into bit D0. The asserting and de-asserting conditions of this bit are as given below. The FIFOs of EP1, EP2, EP4, and EP5 have a 2-layer structure and also there are independent packet ready bits for layer A and layer B. The switching between these two layers is done automatically by the ML60852A.
Bit name EPn Receive packet ready (D0) Asserting condition When an error-free packet is received in either layer A or layer B. Operation when asserted The local MCU can read the EP1 Receive FIFO. EP1 is locked in the condition in which data packets have been received by both layer A and layer B. Operation when de-asserted Reception can be made by EP1 when the bit of either layer A or layer B has been reset.
Bit name EPn Receive packet ready (D0)
De-asserting condition When the local MCU has reset (written a "1" in) the bits of both layer A and layer B.
EP1,2,4,5 Transmit packet ready bit (D1): This bit can be read by the local MCU. Also, this bit can be made "1" by writing a "1" into bit D1. The asserting and de-asserting conditions of this bit are as given below. The FIFO of EP1 has a 2-layer structure and also there are independent packet ready bits for layer A and layer B. The switching between these two layers is done automatically by the ML60852A.
Bit name Asserting condition bits of both layer A and layer B. (2)When the local MCU has set the bits of either layer A or layer B. Bit name De-asserting condition Operation when de-asserted Operation when asserted Transmission can be made from EP1 when either layer A or layer B has been asserted. EPn Transmit packet ready (D1) (1) When the local MCU has set the
EPn Transmit packet ready (D1) When an ACK message is received EP1 is locked when transmit data has from the host for the data transmission not been prepared for both layer A and layer B. to either layer A or layer B.
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EP3 Status Register (EP3STAT)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 EP3 Receive packet ready (Read/Reset) EP3 Transmit packet ready (Read/Set) D1 0 0 D0 0 0 0 x 63 Bit map See below
This register is valid only when EP3 has been set for bulk or interrupt transfer. EP3 Receive packet ready bit (D0): This bit can be read by the local MCU. Also, this bit can be made "0" by writing a "1" into bit D0. The asserting and de-asserting conditions of this bit are as given below.
Bit name Asserting condition Operation when asserted
EP3 Receive packet ready (D0) When an error-free packet is received. EP3 is locked. Bit name De-asserting condition Operation when de-asserted
EP3 Receive packet ready (D0) When the local MCU has reset (written Reception can be made by EP3. a "1" in) this bit.
EP3 Transmit packet ready bit (D1): This bit can be read by the local MCU. Also, this bit can be made "1" by writing a "1" into this bit. The asserting and de-asserting conditions of this bit are as given below.
Bit name Asserting condition Operation when asserted
EP3 Transmit packet ready (D1) When the local MCU has set (write `1') When an IN token is received from the this bit. host, ML60852A will automatically transmit its EP3FIFO transmit data on to the USB bus. Bit name De-asserting condition Operation when de-asserted
EP3 Transmit packet ready (D1) After a hardware reset, bus reset, or Data can be written to the Tx FIFO of when an ACK is received in response EP3. to succussful data transmission.
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EP4, 5 Payload MSB Registers (EP4, 5PLDMSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 EP Payload MSB D1 0 0 D0 0 0 0 x 6C, 6D 10-Bit or 9-bit data Read/Write
The higher-order 6 bits of EP4PLDMSB are fixed at "0" and the higher-order 7 bits of EP5PLDMSB are fixed at "0".
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EP4, 5 Receive Byte MSB Counter Registers (EP4, 5RXCNTMSB)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 EP Receive byte count MSB D1 0 0 D0 0 0 0 x 74, 75 10-Bit or 9-bit data Read only
The higher-order 6 bits of EP4RXCNTMSB are fixed at "0" and the higher-order 7 bits of EP5RXCNTMSB are fixed at "0".
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Transmit Packet Ready Control Register (TXPKTCONT)
Address Type Access type D7 After a hardware reset After a bus reset Definition 0 0 0 D6 0 D5 0 D4 0 D3 0 0 D2 0 D1 0 D0 0 0 Write Disable EP1 Transmit Packet Ready Control bit EP2 Transmit Packet Ready Control bit Write Disable 0 x 3E Bit map Read/Write
The previous value is retained
EP4 Transmit Packet Ready Control bit EP5 Transmit Packet Ready Control bit Write Disable Write Disable
EPn (n=1,2,4,5) transmit packet ready control bit This register is mainly used for controlling the double-layered FIFO structure operation of ML60852A. Writing a "1" into this bit controls the assert and de-assert conditions of the EP1,EP2,EP4,EP5 transmit packet ready interrupts and operations of bits corresponding to EPn (n=1,2,4,5) status register. For EPn (n=1,2,4,5) status register, see "INTERNAL REGISTERS". This register controls the above conditions and bit operations only during transmission (from ML60852A to HOST) and does not control them during reception (from HOST to ML60852A).
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* Relationship between the transmit FIFO status, register status of each EP and INTR signal Note: The following table assumes that the transmit packet ready status bit (D1 of EPnSTAT) is set (to `1') immediately after writing transmit data to each layer of the EPnFIFO.
Register status of each EP Trnsmit FIFO status Both layers are not empty One layer is empty and Other layer is not empty Both layers are empty Packet ready interrupt enable bit = 1 Transmit packet ready control bit = 0 INTR signal is de-asserted INTR signal is asserted INTR signal is asserted Register status of each EP Packet ready interrupt enable bit = 1 Transmit packet ready control bit = 1 INTR signal is de-asserted INTR signal is de-saaerted INTR signal is asserted
* Definition of transmit FIFO "empty" When one of the following two conditions is satisfied, transmit FIFO is empty. (1) In the early transmit stage just after the corresponding endpoint configuration, the local MCU has not written a "1" into the D1 bit of the EPnSTAT register yet. (2) The transmit data written by the local MCU is transferred to HOST and an ACK signal is returned from HOST.
* When the packet ready interrupt enable bit of the corresponding EP is de-asserted, the INTR signal is de-asserted irrespective of the status of transmit FIFO. (When other interrupt factor is generated, the INTR signal is asserted.) The interrupt factor of the transmit packet ready interrupt can be changed by using the transmit packet ready control bit. For instance, if one layer of transmit FIFO is empty and other layer is not empty,
* The asserted INTR signal is de-asserted by changing the transmit packet ready control bit to "1" from "0". * The de-asserted INTR signal is asserted by changing the transmit packet ready control bit to "0" from "1".
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TIMING DIAGRAM
READ Timing (1) (Address Separate, ADSEL =0)
Parameter Address Setup Time Address (CS) Hold Time Read Data Delay Time Read Data Hold Time Recovery Time FIFO Access Time Symbol t1 t2 t3 t4 t5 t6 FIFO READ FIFO READ Load 20 pF Condition Min. 0 0 -- 0 63 63 Max. -- -- 46 21 -- -- Unit ns ns ns ns ns ns (3) (3) (2) (1) Note
Notes: (1) t3 is defined depending upon CS or RD which becomes active last. (2) t2 is defined depending upon CS or RD which becomes active first. (3) 3-clock time of oscillation clock (clock period:21 ns). It is required for increment of FIFO.
A7:A0
t
1
t t
6
2
CS +5
t
5
RD 4,
t
3
t
4
AD7:AD0
DATA OUT
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READ Timing (2) (Address/Data Multiplex, ADSEL =1)
Parameter Address (CS) Setup Time Address (CS) Hold Time Read Data Delay Time Read Data Hold Time Recovery Time FIFO Access Time Symbol t1 t2 t3 t4 t5 t6 FIFO READ FIFO READ Load 20 pF Condition Min. 10 0 -- 0 63 63 Max. -- -- 46 21 -- -- Unit ns ns ns ns ns ns (1) (1) Note
Notes: (1) 3-clock time of oscillation clock (clock period:21 ns). It is required for increment of FIFO.
AD7: AD0
ADDRESS
DATA OUT
t1
t2 t4
+5 CS
ALE t3
t5
4, RD
t6
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WRITE Timing (1) (Address Separate, ADSEL =0)
Parameter Address Setup Time Address (CS) Hold Time Write Data Setup Time Write Data Hold Time Recovery Time FIFO Access Time Symbol t1 t2 t4 t5 t6 t7 FIFO WRITE FIFO WRITE Condition Min. 0 0 30 0 63 63 Max. -- -- -- -- -- Unit ns ns ns ns ns ns (1) (1) Note
Note: (1) 3-clock time of oscillation clock (clock period: 21ns). It is required for increment of FIFO.
A7:A0
t1
t2 t7
CS +5
t6
94 WR
t4 AD7:AD0 DATA IN t5
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WRITE Timing (2) (Address/Data Multiplex, ADSEL =1)
Parameter Address (CS) Setup Time Address (CS) Hold Time Write Data Delay Time Write Data Hold Time Recovery Time FIFO Access Time Symbol t1 t2 t3 t4 t5 t6 FIFO WRITE FIFO WRITE Condition Min. 10 0 30 0 63 63 Max. -- -- -- -- -- -- Unit ns ns ns ns ns ns (1) (1) Note
Notes: (1) 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.
AD7: AD0
ADDRESS
DATA IN
t1 CS +5
t2
t4
ALE t3 t5 WR 94
t6
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DMA Transfer Timing (1) ML60852A to Memory (Single Transfer, Single Address Mode)
Parameter DREQ Disable Time DREQ Enable Time DACK Hold Time Read Data Delay Time Data Hold Time Recovery Time Symbol t1 t2 t3 t4 t5 t6 8-bit DMA 16-bit DMA Load 20 pF Condition Load 20 pF Min. -- -- 0 -- 0 63 105 Max. 20 63 -- 46 -- -- -- Unit ns ns ns ns ns ns ns (2) (3) (1) (4) Note
Notes: (1) When in Single Address mode, CS and A6: A0 are ignored. t1 and t4 are defined depending on DACK or RD which becomes active last. (2) 3-clock time of oscillation clock (clock period: 21 ns). (3) 5-clock time of oscillation clock (clock period: 21 ns). (4) It is possible to increase t2 by setting the DMA interval register (DMAINTVL).
DREQ ,4-3
t1 DACK t4
t3
t2
t6
RD 4,
t5
DOUT
DATA OUT
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DMA Transfer Timing (2) ML60852A to Memory (Single Transfer, Dual Address Mode)
Parameter DREQ Disable Time DREQ Enable Time Read Data Delay Time Data Hold Time Recovery Time Symbol t1 t2 t3 t4 t5 8-bit DMA 16-bit DMA Load 20 pF Condition Load 20 pF Min. -- -- -- 0 63 105 Max. 20 63 46 -- -- -- Unit ns ns ns ns ns ns (2) (3) (4) (1) Note
Notes: (1) When in Dual Address mode, the DACK is ignored. t1 and t3 are defined depending on CS or RD which becomes active last. A6: A0 specifies the FIFO address. Refer to READ Timing (1) for Address Setup Time and Address Hold Time. (2) 3-clock time of oscillation clock (clock period: 21 ns). (3) 5-clock time of oscillation clock (clock period: 21 ns). (4) It is possible to increase t t2 by setting the DMA interval register (DMAINTVL).
A7: A0
DREQ ,4-3 CS +5
t1
t2
t5
4, RD
t3
t4
DOUT
DATA OUT
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DMA Transfer Timing (3) ML60852A to Memory (Demand Transfer, Single Address Mode)
Parameter DREQ Disable Time DACK Hold Time Read Data Delay Time Data Hold Time Recovery Time Symbol t1 t2 t3 t4 t5 8-bit DMA 16-bit DMA Load 20 pF Condition Load 20 pF Min. -- 0 -- 0 63 105 Max. 20 -- 46 -- -- -- Unit ns ns ns ns ns ns (2) (3) (1) Note
Notes: (1) When in Single Address mode, t3 is defined depending on DACK or RD which becomes active last. A6: A0 and CS are ignored. (2) 3-clock time of oscillation clock (clock period: 21 ns). (3) 5-clock time of oscillation clock (clock period: 21 ns).
,4-3 DREQ
t1 DACK t5 t2
RD 4,
t3 DOUT t4
Last Packet Read
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DMA Transfer Timing (4) ML60852A to Memory (Demand Transfer, Dual Address Mode)
Parameter DREQ Disable Time CS Hold Time Read Data Delay Time Data Hold Time Recovery Time Symbol t1 t2 t3 t4 t5 8-bit DMA 16-bit DMA Load 20 pF Condition Load 20 pF Min. -- 0 -- 0 63 105 Max. 20 -- 46 -- -- -- Unit ns ns ns ns ns ns (2) (3) (1) Note
Notes: (1) When in Dual Address mode, the DACK is ignored. t3 is defined depending on CS or RD which becomes active last. A6: A0 specifies the FIFO address. Refer to READ Timing (1) for Address Setup Time and Address Hold Time. (2) 3-clock time of oscillation clock (clock period: 21 ns). (3) 5-clock time of oscillation clock (clock period: 21 ns).
AD7: A0
DREQ ,4-3
t1
CS +5
t5 t2
RD 4,
t4 t3 DOUT Last Packet Read
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DMA Transfer Timing (5) Memory to ML60852A (Single Transfer, Single Address Mode)
Parameter DREQ Disable Time DREQ Enable Time FIFO Access Time DACK Hold Time Write Data Setup Time Write Data Hold Time Recovery Time Symbol t1 t2 t3 t4 t5 t6 t7 8-bit DMA 16-bit DMA FIFO WRITE Condition Load 20 pF Min. -- -- 42 0 30 5 63 105 Max. 20 63 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns (2) (3) (4) (1) Note
Notes: (1) (2) (3) (4)
When in Single Address mode, CS and A6: A0 are ignored. 3-clock time of oscillation clock (clock period: 21 ns). 5-clock time of oscillation clock (clock period: 21 ns). It is possible to increase t2 by setting the DMA interval register (DMAINTVL).
DREQ ,4-3
t1 DACK t3
t4
t2
94 WR
t5 DIN t6
t7
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DMA Transfer Timing (6) Memory to ML60852A (Single Transfer, Dual Address Mode)
Parameter DREQ Disable Time DREQ Enable Time FIFO Access Time Write Data Setup Time Write Data Hold Time Recovery Time Symbol t1 t2 t3 t4 t5 t6 8-bit DMA 16-bit DMA FIFO WRITE Condition Load 20 pF Min. -- -- 42 30 5 63 105 Max. 20 63 -- -- -- -- -- Unit ns ns ns ns ns ns ns (2) (3) (4) (1) Note
Notes: (1) When in Dual Address mode, the DACK is ignored. t1 and t3 are defined depending on CS or WR which becomes active last. Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time. (2) 3-clock time of oscillation clock (clock period: 21 ns). (3) 5-clock time of oscillation clock (clock period: 21 ns). (4) It is possible to increase t2 by setting the DMA interval register (DMAINTVL).
A7: A0
DREQ ,4-3
t1
t2
CS +5
t3 t6
WR RD 4,
t4 DIN t5
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DMA Transfer Timing (7) Memory to ML60852A (Demand Transfer, Single Address Mode)
Parameter DREQ Disable Time FIFO Access Time DACK Hold Time Write Data Setup Time Write Data Hold Time Recovery Time Symbol t1 t2 t3 t4 t5 t6 8-bit DMA 16-bit DMA Condition Load 20 pF FIFO WRITE Min. -- 42 0 30 5 63 105 Max. 20 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns (2) (3) (1) Note
Notes: (1) When in Single Address mode,A6: A0 and CS are ignored. t2 is defined depending on DACK or WR which becomes active last. (2) 3-clock time of oscillation clock (clock period: 21 ns). (3) 5-clock time of oscillation clock (clock period: 21 ns).
DREQ ,4-3
t1 DACK t2 t6 t3 (Note) t4 DIN t5 Last Packet Write
94 WR
(Note) The last Write to reach the byte size (maximum packet size) specified by the EP1 Payload Register. To terminate DMA transfer before reaching the maximum packet size, set EP1 Packet Ready by writing "1"to the EP1 Endpoint Packet Ready bit.
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DMA Transfer Timing (8) Memory to ML60852A (Demand Transfer, Dual Address Mode)
Parameter DREQ Disable Time FIFO Access Time CS Hold Time Write Data Setup Time Write Data Hold Time Recovery Time Symbol t1 t2 t3 t4 t5 t6 8-bit DMA 16-bit DMA Condition Load 20 pF FIFO WRITE Min. -- 42 0 30 5 63 105 Max. 20 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns (2) (3) (1) Note
Notes: (1) When in Dual Address mode, the DACK is ignored. A6: A0 specifies the FIFO address. Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time. t2 is defined depending on CS or WR which becomes active last. (2) 3-clock time of oscillation clock (clock period: 21 ns). (3) 5-clock time of oscillation clock (clock period: 21 ns).
A7: A0
DREQ ,4-3
t1
CS +5
t2 t6 t3
94 WR
t4 t5
DIN
(Note) Refer to the previous page.
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REVISION HISTORY
Date Nov. 2001 Changes compared to previous version -The guaranteed operating temperature range has been changed from 0C ~ 70C to
-20C ~ +80C
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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